Vertical synchronizing signal generation apparatus and video signal processing apparatus

ABSTRACT

The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

TECHNICAL FIELD

[0001] The present invention relates to signal processing of equipmenthandling video signals, and more particularly, to a technology of stablyseparating vertical synchronizing (sync) signals of video signals.

BACKGROUND ART

[0002] Equipment for displaying and recording/reproducing video signals,such as TVs and videotape recorders (VTRs), performs signal processingbased on sync signals superimposed on the video signals in theirblanking intervals. Therefore, to ensure stable display andrecording/reproduction, it is required to separate sync signalsinvariably stably, irrespective of the quality of input video signals.Japanese Laid-Open Patent Publication No. 01-71280, for example,discloses that stabilization of a separated horizontal sync signal isimproved by using a horizontal sync signal generated by an automaticfrequency control (AFC) circuit, which is free from excessive or missingsynchronizing pulses, in place of the separated horizontal sync signalitself.

[0003] As for stabilization of a vertical sync signal, also, an exampleusing an AFC circuit is disclosed in Japanese Laid-Open PatentPublication No. 4-188960. FIG. 23 is a block diagram of such aconventional vertical sync signal generator.

[0004] Referring to FIG. 23, a sync signal separation circuit 91receives a video signal including a luminance signal, separates avertical sync signal from the video signal, and outputs the separatedsignal to an AFC circuit 92 and a vertical sync signal detection circuit93. The AFC circuit 92 and a FvVCO circuit 94 constitute a phase lockedloop (PLL) having a feedback loop. The AFC circuit 92 compares the phaseof the vertical sync signal separated by the sync signal separationcircuit 91 with the phase of a signal output from the FvVCO circuit 94,and outputs the resultant phase error to the FvVCO circuit 94. The FvVCOcircuit 94 changes its oscillating frequency according to the phaseerror and outputs a signal having a frequency equal to the verticalfrequency. Therefore, a frequency-stabilized signal can be output fromthe FvVCO circuit 94 even if the vertical sync signal separated by thesync signal separation circuit 91 has excessive or missing synchronizingpulses.

[0005] The vertical sync signal detection circuit 93 detectsexistence/absence of a vertical sync signal and outputs the result to aselector 96 as a selection signal. A FvOSC circuit 95 oscillates infree-run operation, and the output thereof has a frequency stabilized atthe vertical frequency. The FvOSC circuit 95 outputs the generatedsignal to the selector 96. The selector 96 selects one of the outputs ofthe FvVCO circuit 94 and the FvOSC circuit 95 based on the output of thevertical sync signal detection circuit 93, and outputs the result as thevertical sync signal.

[0006] That is, the selector 96 selects and outputs the PLL-stabilizedoutput of the FvVCO circuit 94 when a vertical sync signal in the videosignal is detected by the vertical sync signal detection circuit 93.When no vertical sync signal is detected, the selector 96 selects andoutputs the output of the FvOSC circuit 95 stably oscillating infree-run operation.

[0007] Problem to be Solved

[0008] In the configuration described above, switching is made betweenthe signal synchronizing with the vertical sync signal of the inputvideo signal and the signal output from the circuit oscillating infree-run operation, according to existence/absence of a vertical syncsignal in the input video signal. Therefore, immediately after theswitching, the pulse interval of the vertical sync signal losescontinuity, causing synchronization disorder.

[0009] In still reproduction in a VTR, for example, the input videosignal includes a vertical sync signal, but the vertical sync signal hasperiods changing alternately every field. When such a video signal isinput, the selector 96 selects and outputs the output of the FvVCOcircuit 94. Since the PLL averages the frequency of the vertical syncsignal of the input video signal, the output of the FvVCO circuit 94goes out of synchronization with the input video signal.

DISCLOSURE OF THE INVENTION

[0010] An object of the present invention is providing a vertical syncsignal generator capable of providing a vertical sync signal having astable period and also providing a vertical sync signal synchronizingwith a vertical sync signal contained in an input signal even when thevertical sync signal contained in the input signal has two differentperiods repeated alternately.

[0011] Another object of the present invention is providing a videosignal processor capable of securing invariably stable framesynchronization of a video signal even when a vertical sync signalcontained in an input signal has two different periods repeatedalternately.

[0012] Yet another object of the present invention is providing a videosignal processor capable of providing standard video data completelyconforming to a standard even when a vertical sync signal contained inan input signal has two different periods repeated alternately.

[0013] Yet another object of the present invention is providing avertical sync signal generator capable of providing a vertical syncsignal having a stable period by swiftly drawing the signal intosynchronization with a vertical sync signal contained in the inputsignal even when the input signal goes out of phase.

[0014] The vertical sync signal generator of the present inventionincludes: a vertical sync signal separation circuit for separating avertical sync signal of an input luminance signal and outputting theseparated signal as a first vertical sync signal; an automatic frequencycontrol circuit for receiving the first vertical sync signal, generatinga second vertical sync signal having a repeat frequency correspondingwith an average repeat frequency of the first vertical sync signal, andoutputting the generated signal; a vertical sync signal phase detectioncircuit for detecting whether or not the first vertical sync signal hastwo different periods repeated alternately, and outputting the detectionresult as a decision signal; and a selector for receiving the first andsecond vertical sync signals, selecting the first vertical sync signalwhen the decision signal indicates that the first vertical sync signalhas two different periods repeated alternately and otherwise selectingthe second vertical sync signal, and outputting the selected signal.

[0015] According to the invention described above, it is possible toprovide a vertical sync signal having a stable frequency and no pulsemissing. When the first vertical sync signal contained in an inputsignal has two different periods repeated alternately, the firstvertical sync signal, not the second vertical sync signal, is selected.Therefore, a vertical sync signal invariably synchronizing with theinput luminance signal can be obtained. In addition, since the first andsecond vertical sync signal synchronize with each other, no disorder ofsynchronization occurs during switching of the selected vertical syncsignal.

[0016] Preferably, the automatic frequency control circuit includes: anintegrator circuit of m bits (m is a natural number) for accumulatinginput values; a phase comparator circuit for sampling an output of theintegrator circuit at the timing of the first vertical sync signal andoutputting a difference between a sampled value and a predeterminedvalue; a low pass filter for allowing passing of a low-frequencycomponent out of the output of the phase comparator circuit; an addercircuit for adding a constant to an output of the low pass filter andoutputting the result to the integrator circuit; and a differentialcircuit for differentiating the most significant bit of the integratorcircuit and outputting the second vertical sync signal at a timing ofthe resultant edge.

[0017] Preferably, the vertical sync signal phase detection circuitincludes: a V period counter reset at the timing of the first verticalsync signal, for counting the number of pulses of a clock and outputtingthe count value; a first hold circuit for latching the output of the Vperiod counter at the timing of the first vertical sync signal,outputting the latched value, and holding the output until nextlatching; a first subtractor circuit for calculating a differencebetween the output of the V period counter and the output of the firsthold circuit and outputting the result; a first absolute value circuitfor obtaining an absolute value of the output of the first subtractorcircuit and outputting the result; a second hold circuit for latchingthe output of the first absolute value circuit at the timing of thefirst vertical sync signal, outputting the latched value, and holdingthe output until next latching; a second subtractor circuit forcalculating a difference between the output of the first absolute valuecircuit and the output of the second hold circuit and outputting theresult; a second absolute value circuit for obtaining an absolute valueof the output of the second subtractor circuit and outputting theresult; a first comparator circuit for comparing the output of the firstabsolute value circuit with a first constant and outputting the result;a second comparator circuit for comparing the output of the secondabsolute value circuit with a second constant and outputting the result;and a logic circuit for conducting logic operation of the output of thefirst comparator circuit and the output of the second comparator circuitand outputting the result as the decision signal.

[0018] The video signal processor of the present invention includes: avertical sync signal generator; a horizontal sync signal separationcircuit for separating a horizontal sync signal of an input luminancesignal and outputting the separated signal; and a frame sync circuithaving a frame memory, for generating a write address in a predeterminedorder based on an output of the vertical sync signal generator, thehorizontal sync signal and a write clock, and writing an input videosignal into the frame memory according to the write address, as well asgenerating a read address in the same order as the order of the writeaddress based on a read clock, reading the signal from the frame memoryaccording to the read address, and outputting the read signal as astandard video signal, wherein the vertical sync signal generatorincludes: a vertical sync signal separation circuit for separating avertical sync signal of the input luminance signal and outputting theseparated signal as a first vertical sync signal; an automatic frequencycontrol circuit for receiving the first vertical sync signal, generatinga second vertical sync signal having a repeat frequency correspondingwith an average repeat frequency of the first vertical sync signal, andoutputting the generated signal; a vertical sync signal phase detectioncircuit for detecting whether or not the first vertical sync signal hastwo different periods repeated alternately, and outputting the detectionresult as a decision signal; and a selector for receiving the first andsecond vertical sync signals, selecting the first vertical sync signalwhen the decision signal indicates that the first vertical sync signalhas two different periods repeated alternately and otherwise selectingthe second vertical sync signal, and outputting the selected signal, andwhen the rate at which the write address changes and the rate at whichthe read address changes are different from each other, the frame synccircuit controls the write into the frame memory or the read from theframe memory so that during read of a signal of a given frame from theframe memory, read of a signal of a frame other than the given framecaused by address overtaking does not occur.

[0019] According to the present invention described above, by using thevertical sync signal generator described above, a video signal displayedis free from inter-field deviation even when the vertical sync signalcontained in the input signal has two different periods repeatedalternately, and thus an invariably frame-synchronizing video signal canbe obtained. In addition, during read of a signal of a given frame fromthe frame memory, no signal of a frame other than the given frame willbe read, which may otherwise occur due to address overtaking.Accordingly, discontinuity of an image in a read frame is prevented.

[0020] Preferably, the frame sync circuit has at least two framememories, and includes: a write control circuit for generating a writeselection signal for selecting a frame memory into which a signal iswritten, from the two frame memories, and the write address for theselected frame memory, based on the output of the vertical sync signalgenerator, the horizontal sync signal and the write clock, andoutputting the generated signal and address; a read control circuit forcounting the read clock, generating the read address for the two framememories according to the resultant count value, and outputting thegenerated address; and a skip/hold control circuit for generating askip/hold control signal for selecting a frame memory from which asignal is read, based on the trends of changes of the write address andthe read address, and outputting the generated signal, and the framesync circuit writes an input video signal into the frame memory selectedwith the write selection signal according to the write address, and alsoreads a signal from the frame memory selected with the skip/hold controlsignal according to the read address and outputs the signal as thestandard video signal.

[0021] Preferably, the frame sync circuit includes: a line memory fordelaying an input video signal by a time corresponding to apredetermined number of lines and outputting the delayed signal; a writecontrol circuit for generating the write address for the frame memorybased on the output of the vertical sync signal generator, thehorizontal sync signal and the write clock, and outputting the generatedaddress; a read control circuit for counting the read clock, generatingthe read address for the frame memory according to the resultant countvalue, and outputting the generated address; and a skip/hold controlcircuit for generating a skip/hold control signal for controlling sothat either one of the input video signal and the output of the linememory is selected based on a difference between the write address andthe read address and written into the frame memory, the frame synccircuit writes one of the input video signal and the output of the linememory selected with the skip/hold control signal into the frame memoryaccording to the write address, and also reads a signal from the framememory according to the read address and outputs the signal as thestandard video signal.

[0022] The video signal processor described above preferably furtherincludes a data multiplexer circuit for adding a data group representinga start mark, an end mark and a blanking time to data of each line ofthe standard video signal output from the frame sync circuit.

[0023] According to the invention described above, the standard videodata completely conforming to a digital signal standard can be obtainedeven when the vertical sync signal contained in an input signal has twodifferent periods repeated alternately.

[0024] The vertical sync signal generator of the present inventionincludes: a vertical sync signal separation circuit for separating avertical sync signal of an input luminance signal and outputting theseparated signal as a first vertical sync signal; an automatic frequencycontrol circuit for receiving the first vertical sync signal, generatinga second vertical sync signal having a repeat frequency correspondingwith an average repeat frequency of the first vertical sync signal and aphase error signal indicating a phase difference between the firstvertical sync signal and the second vertical sync signal, and outputtingthe generated signals; a vertical sync signal phase detection circuitfor detecting whether or not the first vertical sync signal and thesecond vertical sync signal are out of phase with each other based onthe phase error signal, and outputting the detection result as adecision signal; and a selector for receiving the first and secondvertical sync signals, selecting the first vertical sync signal when thedecision signal indicates that the first vertical sync signal and thesecond vertical sync signal are out of phase with each other andotherwise selecting the second vertical sync signal, and outputting theselected signal.

[0025] According to the invention described above, when the firstvertical sync signal contained in an input signal is out of phase withthe second vertical sync signal during power-on, scene switching and inother occasions, the first vertical sync signal, not the second verticalsync signal, is selected and output. This makes it possible to provide avertical sync signal having a stable frequency and no pulse missing, andalso provide a vertical sync signal invariably synchronizing with theinput luminance signal.

[0026] Preferably, the automatic frequency control circuit includes: anintegrator circuit of m bits for accumulating input values; a phasecomparator circuit for sampling an output of the integrator circuit atthe timing of the first vertical sync signal and outputting a differencebetween a sampled value and a predetermined value as the phase errorsignal; a first low pass filter for allowing passing of a low-frequencycomponent out of the phase error signal; a second low pass filter forallowing passing of the low-frequency component and a component having ahigher frequency than the low-frequency component out of the phase errorsignal; a filter selector for selecting an output of the second low passfilter when the decision signal indicates that the first vertical syncsignal and the second vertical sync signal are out of phase with eachother and otherwise selecting an output of the first low pass filter,and outputting the selected signal; an adder circuit for adding aconstant to the output of the filter selector and outputting the resultto the integrator circuit; and a differential circuit fordifferentiating the most significant bit of the integrator circuit andoutputting the second vertical sync signal at the timing of theresultant edge.

[0027] According to the invention described above, when the firstvertical sync signal and the second vertical sync signal are out ofphase with each other, the output of the low pass filter having fastertransient response is selected. This enables swift drawing of the secondvertical sync signal into synchronization with the first vertical syncsignal.

[0028] Preferably, the vertical sync signal phase detection circuitincludes: an absolute value circuit for obtaining an absolute value ofthe phase error signal and outputting the result; a hold circuit forlatching the output of the absolute value circuit at the timing of thefirst vertical sync signal, outputting the latched value, and holdingthe output until next latching; a lockout comparator circuit forcomparing the output of the hold circuit with a first constant andoutputting the comparison result; a lockout counter for counting thenumber of pulses of the first vertical sync signal when the output ofthe lockout comparator circuit indicates that the output of the absolutevalue circuit is equal to or larger than the first constant, andoutputting the resultant count value; a lockout decision circuit foroutputting a lockout differential pulse when the count value of thelockout counter is equal to a second constant; a lock-in comparatorcircuit for comparing the output of the hold circuit with a thirdconstant and outputting the comparison result; a lock-in counter forcounting the number of pulses of the first vertical sync signal when theoutput of the lock-in comparator circuit indicates that the output ofthe absolute value circuit is equal to or smaller than the thirdconstant, and outputting the resultant count value; a lock-in decisioncircuit for outputting a lock-in differential pulse when the count valueof the lock-in counter is equal to a fourth constant; and a logiccircuit for outputting the decision signal indicating that the firstvertical sync signal and the second vertical sync signal are out ofphase with each other when the lockout decision circuit outputs thelockout differential pulse, and outputting the decision signalindicating that the first vertical sync signal and the second verticalsync signal are not out of phase with each other when the lock-indecision circuit outputs the lock-in differential pulse.

[0029] According to the present invention described above, the lock-indifferential pulse is output only after the absolute value of the phaseerror signal is kept small for a certain time period, and in response tothis, the decision signal is changed to the level indicating that thefirst and second vertical sync signals are not out of phase with eachother. Therefore, the selector switches the selection from the firstvertical sync signal to the second vertical sync signal in the statethat the first and second vertical sync signals are in synchronizationwith each other. Thus, no disorder occurs in the vertical sync signaloutput from the selector.

[0030] Effect of the Invention

[0031] As described above, according to the present invention, avertical sync signal having a stable period can be provided. Inaddition, an invariably frame-synchronizing video signal can be providedeven when the vertical sync signal contained in an input signal has twodifferent periods repeated alternately or when the input vertical syncsignal abruptly goes out of phase. Therefore, standard video datacompletely conforming to a digital signal standard can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a block diagram of a vertical sync signal generator ofEmbodiment 1 of the present invention.

[0033]FIG. 2(a) is a graph showing the waveform of a luminance signalduring a vertical blanking interval and the timings of separated syncsignals for an odd field.

[0034]FIG. 2(b) is a graph showing the waveform of a luminance signalduring a vertical blanking interval and the timings of separated syncsignals for an even field.

[0035]FIG. 3 is a block diagram of an example of an AFC circuit in FIG.1.

[0036]FIG. 4(a) is a timing chart showing operation of the AFC circuitin FIG. 1 in the case that the vertical sync signal VS has a constantperiod T.

[0037]FIG. 4(b) is a timing chart showing operation of the AFC circuitin FIG. 1 in the case that the vertical sync signal VS has two differentperiods T and T′ repeated alternately.

[0038]FIG. 5 is a block diagram of an example of a vertical sync signalphase detection circuit in FIG. 1.

[0039]FIG. 6 is a view showing values output from respective componentsof the vertical sync signal phase detection circuit.

[0040]FIG. 7 is a block diagram of a video signal processor ofEmbodiment 2 of the present invention.

[0041]FIG. 8(a) is a graph showing examples of timings of a videosignal, a vertical sync signal GVS and a horizontal sync signal HS inputinto a frame sync circuit in FIG. 7.

[0042]FIG. 8(b) is a graph showing examples of signals output from awrite control circuit in FIG. 7.

[0043]FIG. 8(c) is a graph showing examples of signals output from aread control circuit in FIG. 7.

[0044]FIG. 9(a) is a graph demonstrating operation of a skip/holdcontrol circuit in FIG. 7 in the case that write operation overtakesread operation.

[0045]FIG. 9(b) is a graph demonstrating operation of the skip/holdcontrol circuit in FIG. 7 in the case that read operation overtakeswrite operation.

[0046]FIG. 10(a) is a view demonstrating a write state of a video signalstored in frame memories in FIG. 7.

[0047]FIG. 10(b) is a view demonstrating images output from a videosignal processor including the conventional vertical sync signalgenerator of FIG. 23 in place of the vertical sync signal generator ofFIG. 1.

[0048]FIG. 10(c) is a view demonstrating images output from the videosignal processor of FIG. 7.

[0049]FIG. 11 is a block diagram of a video signal processor of analteration to Embodiment 2 of the present invention.

[0050]FIG. 12(a) is a graph demonstrating operation of a skip/holdcontrol circuit in FIG. 11 in the case that write operation overtakesread operation.

[0051]FIG. 12(b) is a graph demonstrating operation of the skip/holdcontrol circuit in FIG. 11 in the case that read operation overtakeswrite operation.

[0052]FIG. 13 is a flowchart showing a flow of processing by a framesync circuit in FIG. 11.

[0053]FIG. 14 is a block diagram of a video signal processor ofEmbodiment 3 of the present invention.

[0054]FIG. 15(a) is a view showing 1716 pieces of data for one lineaccording to the digital video signal standard Rec. 656.

[0055]FIG. 15(b) is a view demonstrating EAV and SAV according to thedigital video signal standard Rec. 656.

[0056]FIG. 16 is a block diagram of a vertical sync signal generator ofEmbodiment 4 of the present invention.

[0057]FIG. 17 is a block diagram of an example of an AFC circuit in FIG.16.

[0058]FIG. 18 is a block diagram of an example of a vertical sync signalphase detection circuit in FIG. 16.

[0059]FIG. 19 is a timing chart showing generation of a lockoutdifferential pulse by a vertical sync signal phase detection circuit inthe case that a vertical sync signal VS goes out of phase largely.

[0060]FIG. 20 is a timing chart showing operation of the vertical syncsignal phase detection circuit in the case that noise enters thevertical sync signal VS.

[0061]FIG. 21 is a timing chart showing generation of a lock-indifferential pulse by the vertical sync signal phase detection circuitin the case that the vertical sync signal VS goes out of phase largely.

[0062]FIG. 22 is a timing chart showing operation of a logic circuit inFIG. 18.

[0063]FIG. 23 is a block diagram of a conventional vertical sync signalgenerator.

BEST MODE FOR CARRYING OUT THE INVENTION

[0064] Hereinafter, embodiments of the present invention will bedescribed with reference to the relevant drawings.

EMBODIMENT 1

[0065]FIG. 1 is a block diagram of a vertical sync signal generator ofEmbodiment 1 of the present invention. A vertical sync signal generator10 of FIG. 1 includes a vertical sync signal separation circuit 11, anautomatic frequency control (AFC) circuit 20, a vertical sync signalphase detection circuit 30 and a selector 12.

[0066] Assume that a luminance signal input into the vertical syncsignal generator 10 of FIG. 1 is one separated from a video signal ofthe National Television System Committee (NTSC) system and that a clockhaving a frequency fs is input into the vertical sync signal separationcircuit 11, the AFC circuit 20, the vertical sync signal phase detectioncircuit 30 and the selector 12.

[0067] The vertical sync signal separation circuit 11 separates a firstvertical sync signal VS superimposed on the input luminance signalduring each vertical blanking interval, and outputs the separated signalto the AFC circuit 20, the vertical sync signal phase detection circuit30 and the selector 12. The AFC circuit 20, provided with a phase lockedloop (PLL), generates a second vertical sync signal AFCVS that roughlysynchronizes with the vertical sync signal VS and has a repeat frequencycorresponding with the average repeat frequency of the vertical syncsignal VS, and outputs the generated signal to the selector 12. Thevertical sync signal phase detection circuit 30 outputs a decisionsignal DS corresponding to the state of the vertical sync signal VS tothe selector 12. The selector 12 selects either one of the vertical syncsignal VS and the vertical sync signal AFCVS according to the decisionsignal DS, and outputs the result as a vertical sync signal GVS.

[0068] Hereinafter, operation of the vertical sync signal generator 10of Embodiment 1 of the present invention will be described.

[0069]FIG. 2(a) is a graph showing the waveform of the luminance signalduring a vertical blanking interval and the timings of separated syncsignals for an odd field. FIG. 2(b) is a graph showing the waveform ofthe luminance signal during a vertical blanking interval and the timingsof separated sync signals for an even field. The time length of threelines from the start of the fourth line in the odd field and the timelength of three lines from the center of the 266th line in the evenfield respectively constitute a vertical sync pulse period. The verticalsync signal separation circuit 11 detects such a vertical sync pulseperiod and outputs a pulse of the vertical sync signal VS at the timingof the start of the vertical sync pulse period.

[0070]FIG. 3 is a block diagram of an example of the AFC circuit 20 inFIG. 1. As shown in FIG. 3, the AFC circuit 20 includes a phasecomparator circuit 21, a low pass filter (LPF) 22, an adder circuit 23,an integrator circuit 24 and a differential circuit 25.

[0071] The phase comparator circuit 21 samples an output S of theintegrator circuit 24 at the timing of each pulse of the vertical syncsignal VS, subtracts the sampled value from D/2, for example, whereD=2^(m) (m is a natural number), and outputs the result. The LPF 22,which is a complete integral type LPF, for example, allows passing ofonly a component having a frequency equal to or less than a givenfrequency out of the output of the phase comparator circuit 21, andoutputs the result to the adder circuit 23.

[0072] The adder circuit 23 adds a constant X to the output of the LPF22, and outputs the result to the integrator circuit 24. The integratorcircuit 24, which is adapted to operation of m-bit width, accumulatesthe output of the adder circuit 23 and outputs the result S to the phasecomparator circuit 21 and the differential circuit 25.

[0073] The differential circuit 25 outputs a pulse as the vertical syncsignal AFCVS when the output S of the integrator circuit 24 reaches D/2.For example, the differential circuit 25 detects a timing at which themost significant bit (MSB) of the output S of the integrated circuit 24changes from “L” to “H” (“L” and “H” respectively represent logical lowand high potentials), and outputs a pulse at the timing of thedetection.

[0074]FIG. 4(a) is a timing chart showing operation of the AFC circuit20 in FIG. 1 performed when the vertical sync signal VS has a constantperiod T. FIG. 4(b) is a timing chart showing operation of the AFCcircuit 20 in FIG. 1 performed when the vertical sync signal VS has twodifferent periods T and T′ repeated alternately.

[0075] As shown in FIG. 4(a), in order to set so that the time periodduring which the integrator circuit 24 increments its count value from 0to reach D-1 and then puts it back to 0 is equal to the period T of thevertical sync signal VS, X=D/(fs×T) should be established.

[0076] The phase comparator circuit 21 samples the output S of theintegrator circuit 24 at the timing of the vertical sync signal VS. Thephase comparator circuit 21 outputs the difference between the sampledvalue and the value D/2 to the LPF 22 as an error signal. For example,if the sampled value is below the value D/2, the error signal has apositive value.

[0077] The LPF 22 smoothes the error signal and outputs the result tothe adder circuit 23. The adder circuit 23 adds the constant X to theoutput of the LPF 22 and outputs the result to the integrator circuit24. The integrator circuit 24 adds the output of the adder circuit 23 tothe accumulated value held therein and again outputs the result to thephase comparator circuit 21. For example, when the error signal is apositive value, the output S of the integrator circuit 24 increasesgreatly, and this speeds up the timing at which the output S reachesD/2.

[0078] As described above, the AFC circuit 20 has a feedback loopserving as a PLL circuit, in which the output S of the integratorcircuit 24 repeats transient response. Therefore, finally, the output Smatches with the vertical sync signal VS in repeat frequency andsynchronizes with the vertical sync signal VS in phase, as shown in FIG.4(a).

[0079] In the case that the period of the vertical sync signal VS isconstant, the vertical sync signal AFCVS synchronizes with the verticalsync signal VS. If a pulse of the vertical sync signal VS isunexpectedly missing, the phase comparator circuit 21 does not samplethe output S of the integrator circuit 24, and thus the outputs of theLPF 22 and the adder circuit 23 remain unchanged. In this case,therefore, the vertical sync signal AFCVS output from the differentialcircuit 25 compensates the missing pulse of the vertical sync signal VS.

[0080] In the case that the period of the vertical sync signal VS isroughly constant but the timing of the vertical sync signal VS variesback and forth repeatedly due to noise and the like, the error of thesampled value from D/2 obtained by the phase comparator circuit 21 isvery small as long as the variation is as small as an amount of severalclocks. Since such an error does not pass through the LPF 22, it won'taffect the input of the integrator circuit 24. Accordingly, the verticalsync signal AFCVS remains stable even when the timing of the verticalsync signal VS repeats a slight variation.

[0081] However a problem arises in the case that the vertical syncsignal VS has two different periods T and T′ repeated alternately asshown in FIG. 4(b) (assume that the difference between the periods T andT′ corresponds to a time period of several scanning lines). If thedifference between the periods T and T′ corresponds to a time periodduring which the integrator circuit 24 increases the output S by 2α, thesampled value from the phase comparator circuit 21 alternately changesbetween D/2+α and D/2−α. Therefore, the output of the LPF 22 is averagedto zero. This results in that, while the average repeat frequency of thevertical sync signal AFCVS as the output of the differential circuit 25matches with that of the vertical sync signal VS, pulses of the verticalsync signal AFCVS are alternately located ahead of and behind those ofthe vertical sync signal VS.

[0082] Thus, the vertical sync signal AFCVS as the output of the AFCcircuit 20 is of no use in the case that the vertical sync signal VS hastwo different periods T and T′ repeated alternately. Detection of such acase is therefore required.

[0083]FIG. 5 is a block diagram of an example of the vertical syncsignal phase detection circuit 30 in FIG. 1. The vertical sync signalphase detection circuit 30 of FIG. 5 includes a V period counter 31, afirst hold circuit 32, a first subtractor circuit 33, a first absolutevalue circuit 34, a second hold circuit 35, a second subtractor circuit36, a second absolute value circuit 37, a first comparator circuit 41, asecond comparator circuit 42 and a logic circuit 43.

[0084] The V period counter 31 receives the vertical sync signal VS anda clock CL having a frequency fs. The V period counter 31 continuescounting pulses of the clock CL, and outputs the count value to the holdcircuit 32 and the subtractor circuit 33. Also, the V period counter 31resets the count value to 0 once a pulse of the vertical sync signal VSis input, and stops incrementing once the count value reaches themaximum countable value. The hold circuit 32 latches the output D1 ofthe V period counter 31 in synchronization with the clock CL once apulse of the vertical sync signal VS is input, and holds the latchedsignal until the hold circuit 32 receives the next pulse of the verticalsync signal VS and further receives a pulse of the clock CL. The holdcircuit 32 outputs the held value to the subtractor circuit 33.

[0085] The subtractor circuit 33 subtracts the output D2 of the holdcircuit 32 from the output D1 of the V period counter 31, and outputsthe result to the absolute value circuit 34. The absolute value circuit34 obtains the absolute value of the output D3 of the subtractor circuit33 and outputs the result to the hold circuit 35, the subtractor circuit36 and the comparator circuit 41. The comparator circuit 41 compares theoutput D4 of the absolute value circuit 34 with a constant A inmagnitude and outputs the result P to the logic circuit 43. The output Pof the comparator 41 is “1” when D4>A and otherwise “0”, for example.The hold circuit 35 latches the output D4 of the absolute value circuit34 in synchronization with the clock CL once a pulse of the verticalsync signal VS is input, and holds the latched signal until the holdcircuit 35 receives a next pulse of the vertical sync signal VS andfurther receives a pulse of the clock CL. The hold circuit 35 outputsthe held value to the subtractor circuit 36.

[0086] The subtractor circuit 36 subtracts the output D5 of the holdcircuit 35 from the output D4 of the absolute value circuit 34, andoutputs the result to the absolute value circuit 37. The absolute valuecircuit 37 obtains the absolute value of the output D6 of the subtractorcircuit 36 and outputs the result to the comparator circuit 42. Thecomparator circuit 42 compares the output D7 of the absolute valuecircuit 37 with a constant B in magnitude and outputs the result Q tothe logic circuit 43. The output Q of the comparator circuit 42 is “1”when D7>B and otherwise “0”, for example. The logic circuit 43 conductslogical operation of the output P of the comparator circuit 41 and theoutput Q of the comparator circuit 42, and outputs the result as thedecision signal DS.

[0087]FIG. 6 shows details of the values output from the components ofthe vertical sync signal phase detection circuit 30. Referring to FIG.6, operation of the vertical sync signal phase detection circuit 30 willbe described. As an example, assume that the clock frequency (samplingfrequency) fs is 27 MHz, and the count values until which the V periodcounter 31 increments during the time period of one scanning line andthe time period of one field are H=1716 and V=450450, respectively.Also, assume that the count values until which the V period counter 31increments during the time periods T and T′ in FIGS. 4(a) and 4(b) are Vand V+H, respectively, and the number of bits of the V period counter is19.

[0088] The following four cases may occur for the period of the verticalsync signal VS. Assume in the following description of these cases thatthe constant A input into the comparator circuit 41 satisfies 0<A<H, andthe constant B input into the comparator circuit 42 satisfies0<B<2¹⁹−V−1.

[0089] (1) Case that the Period of the Vertical Sync Signal VS isConstant

[0090] The output D1 of the V period counter is the constant value V,and thus the output D2 of the hold circuit 32 is also the constant valueV. This gives 0 to all of the output D3 of the subtractor circuit 33,the output D4 of the absolute value circuit 34, the output D5 of thehold circuit 35, the output D6 of the subtractor circuit 36 and theoutput D7 of the absolute value circuit 37. Therefore, P=Q=0.

[0091] (2) Case that the Period of the Vertical Sync Signal VS isRoughly Constant but Varies by Several Clocks

[0092] D1 has an error α1 of several clocks from the constant value V,and D2 also has an error α2 of roughly the same amount. The output D3 ofthe subtractor circuit 33 as the difference between D1 and D2 is sominute compared with the constant value V that D3≈0 may be given.Therefore, D4=D5=D6=D7≈0, and thus P=Q=0.

[0093] (3) Case that a Pulse of the Vertical Sync Signal VS is Missing

[0094] Since no reset is made for the V period counter 31, the output D1stops at 219-1. The output D2=V because the hold circuit 32 holds thevalue received one field earlier. Therefore, D3=D4=2¹⁹−V−1. D5=0 becausethe hold circuit 35 holds the state before the pulse missing. Therefore,D6=D7=2¹⁹−V−1, and thus P=Q=1.

[0095] (4) Case that the Vertical Sync Signal VS has Two DifferentPeriods T and T′ Repeated Alternately

[0096] When D1=V+H and D2=V, D3=V. When D1=V and D2=V+H, D3=−V. Ineither case, D4=H. Therefore, D5=H, and D6=D7=0, and thus P=1 and Q=0.

[0097] The logic circuit 43 determines logical AND of the output P ofthe comparator circuit 41 and the inverted signal of the output Q of thecomparator circuit 42, and outputs the result as the decision signal DS.Thus, the case (4) can be detected because the decision signal DS is “1”only in this case.

[0098] The selector 12 selects the vertical sync signal AFCVS when thedecision signal DS output from the vertical sync signal phase detectioncircuit 30 is “0”, and selects the vertical sync signal VS when thedecision signal DS is “1”, that is, when the vertical sync signal VS hastwo alternately repeated periods, and outputs the selected signal as thevertical sync signal GVS.

[0099] As described above, the vertical sync signal generator of thisembodiment normally outputs the vertical sync signal AFCVS, but outputsthe vertical sync signal VS in place of the vertical sync signal AFCVSwhen it is detected that the vertical sync signal VS has two alternatelyrepeated periods. In this way, a vertical sync signal invariablysynchronizing with the luminance signal of the input video signal can beobtained without occurrence of missing or disorder.

EMBODIMENT 2

[0100]FIG. 7 is a block diagram of a video signal processor ofEmbodiment 2 of the present invention. The video signal processor ofFIG. 7 includes the vertical sync signal generator 10, a horizontal syncsignal separation circuit 14 and a frame sync circuit 50. The frame synccircuit 50 includes a write control circuit 51, a read control circuit52, a skip/hold control circuit 53, frame memories 54 and 55 and aselector 56.

[0101] The vertical sync signal generator 10 and the horizontal syncsignal separation circuit 14 receive a luminance signal. As described inEmbodiment 1, the vertical sync signal generator 10 generates thevertical sync signal GVS invariably synchronizing with the luminancesignal of an input video signal without occurrence of missing ordisorder, and outputs the signal GVS to the write control circuit 51.The horizontal sync signal separation circuit 14 separates a horizontalsync signal HS superimposed on the input luminance signal during eachhorizontal blanking interval, and outputs the result to the writecontrol circuit 51.

[0102] The write control circuit 51 generates a write address W_ADD forwrite in the frame memories 54 and 55, a write enable signal W_ENA and awrite selection signal W_SEL based on the vertical sync signal GVS, thehorizontal sync signal HS and a write clock WCL. The write controlcircuit 51 counts the write clock WCL when the write enable signal W_ENAis active, and uses the resultant count value as the write addressW_ADD, for example. The write control circuit 51 outputs the writeaddress W_ADD and the write selection signal W_SEL to the skip/holdcontrol circuit 53 and the frame memories 54 and 55, and outputs thewrite enable signal W_ENA to the frame memories 54 and 55.

[0103] The read control circuit 52, which receives a read clock RCL,includes a frame counter (F counter, not shown) for counting the readclock RCL every frame period and a line counter (H counter, not shown)for counting the read clock RCL every line period. The F counter and theH counter output the respective count values.

[0104] The read control circuit 52 asserts a read enable signal R_ENAonly when the output of the H counter corresponds to the active time ofthe video signal. The F counter conducts counting when the read enablesignal R_ENA is active. The read control circuit 52 outputs the outputof the F counter to the skip/hold control circuit 53 and the framememories 54 and 55 as a read address R_ADD, and outputs the read enablesignal R_ENA to the frame memories 54 and 55.

[0105] The skip/hold control circuit 53 generates a skip/hold controlsignal SH for controlling the read frame to ensure that, during read ofa signal of a given frame from any of the frame memories 54 and 55, readof a signal of a frame other than the given frame caused by addressovertaking does not occur, that is, to ensure that no discontinuity ofan image occurs in a read frame, and outputs the signal SH to theselector 56. The skip/hold control circuit 53 generally inverts thelevel of the skip/hold control signal SH every read of a frame.

[0106] Each of the frame memories 54 and 55 receives a video signal, andcan store data of one frame of the video signal. The write controlcircuit 51 generates and outputs the write selection signal W_SEL sothat the video signal is alternately written into the frame memories 54and 55 by one frame each. When the write enable signal W_ENA is active,the video signal is written into the frame memory 54 or 55 whicheverselected by the write selection signal W_SEL at the write address W_ADD.

[0107] When the read enable signal R_ENA is active, data at the readaddress R_ADD in the frame memories 54 or 55 are output to the selector56. The selector 56 selects one of the outputs of the frame memories 54and 55 according to the skip/hold control signal SH, and outputs theselected signal as a completely frame-synchronized standard videosignal.

[0108] The operation of the video signal processor having the aboveconfiguration will be described.

[0109]FIG. 8(a) is a graph showing an example of the timings of thevideo signal, the vertical sync signal GVS and the horizontal syncsignal HS input into the frame sync circuit 50. FIG. 8(b) is a graphshowing an example of the signals output from the write control circuit51. FIG. 8(c) is a graph showing an example of the signals output fromthe read control circuit 52.

[0110] In FIGS. 8(b) and 8(c), the ordinate of each of the write addressW_ADD, the read address R_ADD, the F counter output and the H counteroutput represents the value of each signal. Each hatched rectangle ofthe video signal represents an active time of the video signal.

[0111] The write control circuit 51 detects the start line of the videosignal in each field based on the vertical sync signal GVS, and detectseach active time of the video signal based on the horizontal sync signalHS, to assert the write enable signal W_ENA (to “H” in the illustratedexample) permitting write into the frame memory only during the activetime. The write control circuit 51 also generates the write selectionsignal W_SEL to select the memory frame into which the video signal iswritten, out of the two frame memories 54 and 55 of the frame synccircuit 50.

[0112] The write control circuit 51 initializes the write address W_ADDfor the frame memories 54 and 55 at the timing of the vertical syncsignal GVS for an odd field, and sequentially increments the addressevery input of the write clock WCL only for the time period during whichthe write enable signal W_ENA is active. Although the write addressW_ADD is not incremented during each blanking time, it is shown by astraight line in FIG. 8(b) for simplification.

[0113] In FIG. 8(c), the read control circuit 52 asserts the read enablesignal R_ENA (to “H” in the illustrated example) for the time periodduring which the H counter output corresponds to each active time of thevideo signal. The read control circuit 52 sequentially increments theread address R_ADD for the frame memories only for the time periodduring which the read enable signal R_ENA is active. Although the readaddress R_ADD is not incremented during each blanking time, it is shownby a straight line in FIG. 8(c) for simplification.

[0114] In the frame sync circuit 50, the write operation and the readoperation are conducted independently of each other asynchronously.Therefore, the following cases may arise. In one case, the writeoperation may overtake the read operation. That is, write of new datamay be attempted at an address from which old data has not yet beenread. In the other case, the read operation may overtake the writeoperation. That is, read of data may be attempted from an address atwhich new data has not yet been written.

[0115]FIG. 9(a) is a graph demonstrating operation of the skip/holdcontrol circuit 53 in the case that the write operation overtakes theread operation. By the time when the write control circuit 51 finisheswrite of the n-th (n is an integer) frame into the frame memory 54, forexample, the read control circuit 52 has finished read of the (n−2)thframe from the same frame memory 54. Likewise, by the time when thewrite control circuit 51 finishes write of the (n+1)th frame into theframe memory 55, the read control circuit 52 has finished read of the(n−1)th frame from the same frame memory 55. Assume however that duringread of the next n-th frame, the write address W_ADD overtakes the readaddress R_ADD.

[0116] In the event described above, write of the (n+2)th frame will becompleted before the operation of reading the n-th frame is completed.The result is that, although the n-th frame is read until the writeaddress overtakes the read address, data of the (n+2)th frameoverwritten on the data of the n-th frame will be read after thisaddress overtaking. This will cause discontinuity of an image in theread frame.

[0117] The skip/hold control circuit 53 predicts whether or not suchaddress overtaking will occur from the trends of changes of the writeaddress W_ADD and the read address R_ADD. For example, the differencebetween the write address W_ADD and the read address R_ADD may beobtained after the read of the (n−2)th frame and after the read of the(n−1)th frame. From a change in this difference, whether or not thewrite address W_ADD will overtake the read address R_ADD during read ofthe n-th frame can be predicted.

[0118] If predicting that during read of the n-th frame, data will bewritten into the frame memory in which this frame is stored and moreoveraddress overtaking will occur, the skip/hold control circuit 53 does notchange the level of the skip/hold control signal SH. The selector 56therefore does not switch its input, resulting in selecting the (n+1)thframe skipping the n-th frame (that is, “skip” is performed).

[0119] Since the (n+1)th frame exists in the frame memory different fromthe frame memory into which the (n+2)th frame is written, it is notaffected by the address overtaking, if any. In this way, it is possibleto avoid occurrence of such an event that data of the (n+2)th frame maybe read during read of data of the n-th frame since the data of the n-thframe is overwritten with the data of the (n+2)th frame and this maycause discontinuity of an image in a frame.

[0120]FIG. 9(b) is a graph demonstrating operation of the skip/holdcontrol circuit 53 in FIG. 7 in the case that the read operationovertakes the write operation. By the time when the read control circuit52 finishes read of the n-th frame from the frame memory 54, forexample, the write control circuit 51 has finished write of the n-thframe into the same frame memory 54. Likewise, by the time when the readcontrol circuit 52 finishes read of the (n+1)th frame from the framememory 55, the write control circuit 51 has finished write of the(n+1)th frame into the same frame memory 55. Assume however that duringread of the next (n+2)th frame, the read address R_ADD overtakes thewrite address W_ADD.

[0121] In the event described above, operation of reading the (n+2)thframe will be completed before write of the (n+2)th frame is completed.The result is that, although the (n+2)th frame is read until the readaddress overtakes the write address, data of the n-th frame that has notyet been overwritten with data of the (n+2)th frame will be read afterthis address overtaking. This will cause discontinuity of an image inthe read frame.

[0122] The skip/hold control circuit 53 predicts whether or not suchaddress overtaking will occur from the trends of changes of the writeaddress W_ADD and the read address R_ADD. For example, the differencebetween the write address W_ADD and the read address R_ADD may beobtained after the read of the n-th frame and after the read of the(n+1)th frame. From a change in this difference, whether or not the readaddress R_ADD will overtake the write address W_ADD during read of the(n+2)th frame can be predicted.

[0123] If predicting that during read of the (n+2)th frame, data will bewritten into the frame memory in which this frame is stored and moreoveraddress overtaking will occur, the skip/hold control circuit 53 does notchange the level of the skip/hold control signal SH. The selector 56therefore does not switch its input, resulting in selecting the (n+1)thframe again, not the (n+2)th frame (that is, “hold” is performed).

[0124] Since the (n+1)th frame exists in the frame memory different fromthe frame memory into which the (n+2)th frame is written, it is notaffected by the address overtaking, if any. In this way, it is possibleto avoid occurrence of such an event that data of the n-th frame beforebeing overwritten with data of the (n+2)th frame may be read during readof the data of the (n+2)th frame and this may cause discontinuity of animage in a frame.

[0125] As described above, in the video signal processor of FIG. 7, inthe case that the rate at which the write address W_ADD changes isdifferent from the rate at which the read address R_ADD changes, it isensured that during read of a given frame from a frame memory, read of asignal of a frame other than the given frame caused by addressovertaking does not occur. Thus, discontinuity of an image in a readframe is prevented.

[0126]FIG. 10(a) is a view demonstrating the write state of a videosignal stored in the frame memories 54 and 55. Assume herein that theinput video signal is a signal of the NTSC system and that a luminancesignal (Y) and two color-difference signals (Cr and Cb) are multiplexedat a ratio of Y:Cr:Cb=42:2 at a clock of 27 MHz. As a standard, oneframe of the video signal is composed of data of 1716 sampleshorizontally and 525 lines vertically. Among such data, data in theactive times of the video signal includes 1440 samples horizontally and480 lines vertically.

[0127] The operation of the frame memories 54 and 55 will be describedwith reference to FIGS. 7 and 10(a). Assume that the frame memory 54 isselected as the write memory with the write selection signal W_SEL.During each active time of the video signal, the write control circuit51 asserts the write enable signal W_ENA, and while sequentiallyincrementing the write address W_ADD, writes the data of the videosignal in the order of Cr, Y, Cb, Y. Once having written data of 1440samples, the write control circuit 51 negates the write enable signalW_ENA and puts the write address W_ADD in the hold state.

[0128] When the next active time of the video signal comes after thehorizontal blanking interval, the write control circuit 51 again assertsthe write enable signal W_ENA and starts writing while updating thewrite address W_ADD. Once having written data of one frame (1440×480samples), the write control circuit 51 changes the level of the writeselection signal W_SEL, to select the frame memory 55 as the writememory. As in the case of the frame memory 54, data of the next frame ofthe video signal is written into the frame memory 55.

[0129] The read control circuit 52 asserts the read enable signal R_ENAaccording to the H counter output, and while sequentially incrementingthe read address R_ADD, reads the data of the video signal in the orderof Cr, Y, Cb, Y sequentially.

[0130] The case that the vertical sync signal VS has the two differentperiods T and T′ repeated alternately as shown in FIG. 4(b) will bedescribed. FIG. 10(b) is a view showing images output from a videosignal processor using the conventional vertical sync signal generatorof FIG. 23. FIG. 10(c) is a view showing images output from the videosignal processor of FIG. 7.

[0131] When using a vertical sync signal output from the conventionalvertical sync signal generator of FIG. 23, the write control circuit 51determines the start position of each active time of the video signalbased on the vertical sync signal having a roughly constant period,generates the write enable signal W_ENA, and writes data of the videosignal into a frame memory. Therefore, addresses at which the data iswritten are deviated by several lines between the odd field and the evenfield. If the data is read as it is, images deviated vertically fromeach other as shown in FIG. 10(b) are alternately displayed.

[0132] In the video signal processor of this embodiment, in the casedescribed above, the vertical sync signal generator 10 selects thevertical sync signal VS in place of the vertical sync signal AFCVS andoutputs the selected signal as the vertical sync signal GVS. Therefore,the start position of each active time of the video signal can becorrectly determined in both the odd field and the even field, and thusan invariably frame-synchronized video signal free from deviationbetween the fields as shown in FIG. 10(c) can be obtained.

[0133] The write clock WCL and the read clock RCL may be differentclocks independent of each other or may be the same clock.

ALTERATION TO EMBODIMENT 2

[0134]FIG. 11 is a block diagram of a video signal processor of analteration to Embodiment 2. The video signal processor of FIG. 11includes a frame sync circuit 60 in place of the frame sync circuit 50of the video signal processor of FIG. 7. The vertical sync signalgenerator 10 and the horizontal sync signal separation circuit 14 arethe same as those of the video signal processor of FIG. 7, and thereforethe description thereof is omitted here. The frame sync circuit 60 inFIG. 11 includes a write control circuit 61, a read control circuit 62,a skip/hold control circuit 63, a frame memory 64, a line memory 65 anda selector 66.

[0135] The write control circuit 61 is substantially the same as thewrite control circuit 51 except that the write selection signal W_SEL isnot generated. The write control circuit 61 generates a write addressW_ADD for write into the frame memory 64 and a write enable signal W_ENAbased on the vertical sync signal GVS, the horizontal sync signal HS andthe write clock WCL. The write control circuit 61 outputs the writeaddress W_ADD to the skip/hold control circuit 63, and outputs the writeenable signal W_ENA to the frame memory 64.

[0136] The read control circuit 62 receives the read clock RCL. The readcontrol circuit 62, which is substantially the same as the read controlcircuit 52, outputs the output of an F counter to the skip/hold controlcircuit 63 and the frame memory 64 as a read address R_ADD, and outputsa read enable signal R_ENA to the frame memory 64.

[0137] The skip/hold control circuit 63 generates a skip/hold controlsignal SH for controlling input of data into the frame memory 64 toensure that, during read of a signal of a given frame from the framememory 64, read of a signal of a frame other than the given frame causedby address overtaking does not occur, that is, to ensure that nodiscontinuity of an image occurs in a read frame, and outputs the signalto the selector 66.

[0138] The line memory 65 receives a video signal. The line memory 65can store data of 20 lines of the video signal (including data outsidethe active times of the video signal), for example, and operates as aFIFO buffer in which a signal input first is output first. In otherwords, the line memory 65 delays the input video signal by a timecorresponding to 20 lines and outputs the delayed signal to the selector66. The selector 66 also receives the video signal directly. Thecapacity of the line memory 65 is not limited to 20 lines.

[0139] The selector 66 selects either one of the video signal and theoutput of the line memory 65 according to the skip/hold control signalSH, and outputs the result to the frame memory 64. Assume herein thatthe selector 66 selects the video signal when the skip/hold controlsignal SH is “L” and selects the output of the line memory 65 when it is“H”.

[0140] The frame memory 64 stores the output of the selector 66 at thewrite address is W_ADD when the write enable signal W_ENA is active.Also, the frame memory 64 reads data at the read address R_ADD andoutputs the data as a standard video signal when the read enable signalR_ENA is active.

[0141]FIG. 12(a) is a graph demonstrating operation of the skip/holdcontrol circuit 63 in FIG. 11 in the case that the write operationovertakes the read operation. FIG. 12(b) is a graph demonstratingoperation of the skip/hold control circuit 63 in FIG. 11 in the casethat the read operation overtakes the write operation. In the frame synccircuit 60, the write operation and the read operation are conductedindependently of each other asynchronously.

[0142]FIG. 13 is a flowchart showing a flow of processing by the framesync circuit 60 in FIG. 11. The operation of the frame sync circuit 60will be described with reference to FIGS. 12(a), 12(b) and 13.

[0143] First, in step S20, the skip/hold control circuit 63 sets flag=0and the write control circuit 61 sets write address W_ADD=0. In stepS21, the write control circuit 61 asserts the write enable signal W_ENA,to allow the output of the selector 66 to be written into the framememory 64 at the write address W_ADD (assume that SH=0). In step S22,the write control circuit 61 increments the write address W_ADD by one.

[0144] In step S23, the skip/hold control circuit 63 determines whetheror not flag=1. If flag=1, the step proceeds to step S31. Otherwise, thestep proceeds to step S24. In step S24, the skip/hold control circuit 63determines whether or not write address W_ADD=MAX+1. If this equation issatisfied, the step proceeds to step S25. Otherwise, the step returns tostep S21. The value MAX, which is the maximum the write address W_ADDcan normally take, is 1716×525 for a signal of the NTSC system, forexample.

[0145] In FIGS. 12(a) and 12(b), since a range of addresses greater thanMAX−20-odd lines corresponds to a portion outside the active time of thevideo signal, data in this range is not written into the frame memory64.

[0146] In step S25, the skip/hold control circuit 63 sets write addressW_ADD=0. In step S26, the skip/hold control circuit 63 determineswhether or not the read address R_ADD satisfies the condition of beingsmaller than 20 lines or greater than MAX—20 lines. Addresses of 20lines are 1716×20 for a signal of the NTSC system. The reason for using20 lines is that the capacity of the line memory 65 is 20 lines. If thecondition is satisfied, the process proceeds to step S27. Otherwise, theprocess returns to step S21.

[0147] In step S27, the skip/hold control circuit 63 sets flag=1, andthe process returns to step S21. Flag=1 indicates that the differencebetween the write address W_ADD and the read address R_ADD is small, andthus the possibility that the write operation may overtake the readoperation or the read operation may overtake the write operation ishigh.

[0148] In step S31, the skip/hold control circuit 63 determines whetheror not skip/hold control signal SH=0 (that is, “L”). If SH=0, that is,in the case that the selector 66 selects the video signal, the processproceeds to step S32. Otherwise, the process proceeds to step S35. Instep S32, the skip/hold control circuit 63 determines whether or notwrite address W_ADD=MAX. If this equation is satisfied, the processproceeds to step S33. Otherwise, the process returns to step S21.

[0149] The skip/hold control circuit 63 sets write address W_ADD=MAX—20in step S33 and sets flag=0 and SH=1 (that is, “H”) in step S34, andthen the process returns to step S21. That is, the selector 66 isdirected to select the output of the line memory 65. Since the output ofthe line memory 65 is behind the video signal by 20 lines, the writeaddress W_ADD is set behind by 20 lines (see the end of write of framen+3 in FIG. 12(a) and the end of write of frame n+5 in FIG. 12(b)).

[0150] In step S35, the skip/hold control circuit 63 determines whetheror not write address W_ADD=MAX—20 lines. If this equation is satisfied,the step proceeds to step S36. Otherwise, the process returns to stepS21. The skip/hold control circuit 63 sets write address W_ADD=0 in stepS36 and sets flag=0 and SH=0 in step S37, and then the process returnsto step S21. That is, the selector 66 is directed to select the videosignal. Since the video signal is ahead of the output of the line memory65 by 20 lines, write address W_ADD=0 is set. This is equivalent tosetting forward the write address W_ADD by 20 lines (see the end ofwrite of frame n+6 in FIG. 12(a) and the end of write of frame n+2 inFIG. 12(b)). Since the range of addresses greater than MAX—20 linescorresponds to a portion outside the active time of the video signal,data in this range is not written in the frame memory 64. Therefore,write address W_ADD=0 can be set with no influence to display.

[0151] In the case that the write address W_ADD increments faster thanthe read address R_ADD as in FIG. 12(a), the write address W_ADDovertakes the read address R_ADD when the write address W_ADD is setforward by 20 lines (at the end of write of frame n+6). In this event,frame n+7 is read from the frame memory 64 (frame n+6 is skipped).

[0152] In the case that the read address R_ADD increments faster thanthe write address W_ADD as in FIG. 12(b), the read address R_ADDovertakes the write address W_ADD when the write address W_ADD is setback by 20 lines (at the end of write of frame n+5). In this event,frame n+5 is read again from the frame memory 64 (frame n+5 is held).

[0153] As described above, in the video signal processor of FIG. 11, inthe case that the rate at which the write address W_ADD changes isdifferent from the rate at which the read address R_ADD changes, causingaddress overtaking, it is ensured that during read of a signal of agiven frame from the frame memory 64, read of a signal of a frame otherthan the given frame caused by address overtaking does not occur. Thus,discontinuity of an image in a read frame is prevented.

[0154] In the video signal processor of FIG. 11, either one of the videosignal and the output of the line memory 65 is selected and written intothe frame memory 64. Alternately, the output of the frame memory 64 maybe input into the line memory, and either one of the output of the framememory 64 and the output of the line memory may be selected and outputas the standard video signal. In this case, the skip/hold controlcircuit should control the read address R_ADD, not the write addressW_ADD, in the manner described above.

[0155] In Embodiment 2 and the alteration to Embodiment 2, the writeaddress W_ADD and the read address R_ADD were described to incrementfrom 0 sequentially and return to 0 once reaching the maximum. Any orderother than this may be adopted as long as both the write address W_ADDand the read address R_ADD change in the same order. For example, thenumber may decrement from the maximum sequentially and return to themaximum once reaching 0.

EMBODIMENT 3

[0156]FIG. 14 is a block diagram of a video signal processor ofEmbodiment 3 of the present invention. The video signal processor ofFIG. 14 includes the vertical sync signal generator 10, the horizontalsync signal separation circuit 14, the frame sync circuit 50 and a datamultiplexer circuit 100. The vertical sync signal generator 10 issubstantially the same as that described in Embodiment 1, and thehorizontal sync signal separation circuit 14 and the frame sync circuit50 are substantially the same as those described in Embodiment 2.Detailed description thereof is therefore omitted here.

[0157] The data multiplexer circuit 100 receives the read clock RCL aswell as the standard video signal, the H counter output and the Fcounter output from the frame sync circuit 50. The data multiplexercircuit 100 adds a data group defined by a digital video signal standardto the standard video signal output from the frame sync circuit 50, andoutputs standard video data completely conforming to the standard.

[0158] Assume herein that the standard video signal output from theframe sync circuit 50 is a signal of the NTSC system, in which aluminance signal Y and two color-difference signals Cr and Cb aremultiplexed at a ratio of Y:Cr:Cb=4:2:2 at a read clock of 27 MHz. Theluminance signal Y and the two color-difference signals Cr and Cb arerespectively 8-bit data. One frame of the video signal is composed of1716 samples horizontally and 525 lines vertically. Among such data,data in the active times of the video signal includes 1440 sampleshorizontally and 480 lines vertically.

[0159] Assume that the standard video data output from the video signalprocessor of FIG. 14 conforms to the digital video signal standard Rec.ITU-R BT.656-2 (hereinafter, referred to as REC. 656).

[0160]FIG. 15(a) is a view illustrating 1716 pieces of data of one lineaccording to the digital video signal standard Rec. 656. One lineincludes, from the head, 4 T of end mark data (EAV), 268 T of blankingdata, 4 T of start mark data (SAV) and 1440 T of active image data (Tdenotes the sampling period in sampling at 27 MHz). As the blankingdata, 10 h (h denotes hexadecimal notation) is allocated to theluminance signal and 80 h to the color-difference signals. Duringvertical blanking intervals, even the active image data includesrepetition of 80 h (color-difference) and 10 h (luminance).

[0161]FIG. 15(b) is a view demonstrating EAV and SAV according to thedigital video signal standard Rec. 656. Data of EAV and SAV aredifferent among lines. In the NTSC system, data as shown in FIG. 15(b)are used for 1 to 525 lines.

[0162] The F counter counts the line number from 1 to 525 vertically ina cyclic manner, and the H counter counts the data number from 1 to 1716horizontally in a cyclic manner. The standard video signal output fromthe frame sync circuit 50 completely synchronizes with the F counteroutput and the H counter output. The data multiplexer circuit 100decodes the F counter output and the H counter output, and selects fixedvalues stored in a read-only memory (ROM) table during the EAV, SAV andblanking times while selecting the standard video signal during theactive image time, and outputs the result.

[0163] As described above, in the video signal processor of FIG. 14,standard video data completely conforming to a digital video signalstandard can be obtained with the considerably simple circuitconfiguration.

[0164] The frame sync circuit 60 in FIG. 11 may be used in place of theframe sync circuit 50 in FIG. 7.

EMBODIMENT 4

[0165]FIG. 16 is a block diagram of a vertical sync signal generator ofEmbodiment 4 of the present invention. A vertical sync signal generator110 of FIG. 16 includes a vertical sync signal separation circuit 11, anAFC circuit 120, a vertical sync signal phase detection circuit 130 anda selector 12.

[0166] Assume that a luminance signal input into the vertical syncsignal generator 110 of FIG. 16 is one separated from a video signal ofthe NTSC system and that a clock having a frequency fs is input into thevertical sync signal separation circuit 11, the AFC circuit 120, thevertical sync signal phase detection circuit 130 and the selector 12.

[0167] The vertical sync signal separation circuit 11 separates a firstvertical sync signal VS superimposed on the input luminance signalduring each vertical blanking interval, and outputs the separated signalto the AFC circuit 120, the vertical sync signal phase detection circuit130 and the selector 12. The AFC circuit 120, provided with a PLL,generates a second vertical sync signal AFCVS2 that roughly synchronizeswith the vertical sync signal VS and has a repeat frequencycorresponding with the average repeat frequency of the vertical syncsignal VS, and outputs the generated signal to the selector 12. Thevertical sync signal phase detection circuit 130 outputs a decisionsignal DS2 corresponding to the state of the vertical sync signal VS tothe selector 12. The selector 12 selects either one of the vertical syncsignal VS and the vertical sync signal AFCVS2 according to the decisionsignal DS2, and outputs the result as a vertical sync signal GVS2.

[0168]FIG. 17 is a block diagram of an example of the AFC circuit 120 inFIG. 16. As shown in FIG. 17, the AFC circuit 120 includes a phasecomparator circuit 21, LPFs 22 and 122, an adder circuit 23, anintegrator circuit 24, a differential circuit 25 and a selector (filterselector) 126.

[0169] The phase comparator circuit 21, which is substantially the sameas that described with reference to FIG. 3, samples an output S of theintegrator circuit 24 at the timing of each pulse of the vertical syncsignal VS, subtracts the sampled value from value D/2, for example, andoutputs the result to the LPFs 22 and 122 and the vertical sync signalphase detection circuit 130 as a phase error signal PE.

[0170] The LPFs 22 and 122 are complete integral type LPFs, for example.The LPF 22 allows passing of only a component having a frequency equalto or less than a given 5 frequency out of the output of the phasecomparator circuit 21, and outputs the result to the selector 126. TheLPF 122 allows passing of only a component having a frequency equal toor less than a given frequency that is higher than the given frequencyfor the LPF 22, out of the output of the phase comparator circuit 21,and outputs the result to the selector 126. That is, the LPF 122 isfaster in transient response than the LPF 22.

[0171] The selector 126, which receives the decision signal DS2 as acontrol signal, selects either one of the output of the LPF 22 and theoutput of the LPF 122 according to the decision signal DS2 and outputsthe result to the adder circuit 23. The adder circuit 23, the integratorcircuit 24 and the differential circuit 25 are substantially the same asthose described with reference to FIG. 3, and therefore detaileddescription thereof is omitted here. The differential circuit 25 outputsthe resultant vertical sync signal AFCVS2 to the selector 12.

[0172] In the event that the difference in phase between the verticalsync signal VS and the vertical sync signal AFCVS2 is great, such asduring power-on, during switching of the scene and during switching ofthe input video signal, it is desirable for the selector 126 to selectthe output of the LPF 122 that is faster in transient response than theLPF 22, so that the phase of the vertical sync signal AFCVS2 swiftlycomes close to the phase of the vertical sync signal VS.

[0173] However, in the case that the period of the vertical sync signalVS is roughly constant but the timing of the vertical sync signal VSvaries back and forth repeatedly due to noise and the like, the phaseerror signal PE output from the phase comparator circuit 21 passesthrough the LPF 122 and is input into the integrator circuit 24 even ifthe variation is as small as several clocks. As a result, the verticalsync signal AFCVS2 is no more stable. In this case, it is necessary forthe selector 126 to select the output of the LPF 22 that is slower intransient response than the LPF 122 according to the decision signalDS2, to secure stable drawing of the vertical sync signal AFCVS2 intosynchronization.

[0174] To permit the selector 126 to select as described above, thevertical sync signal phase detection circuit 130 should output thedecision signal DS2 indicating that the vertical sync signal AFCVS2 isin the lockout state or lock-in state.

[0175] The lockout state as used herein refers to the state that thevertical sync signal VS and the vertical sync signal AFCVS2 are out ofphase with each other, in which the phase error signal PE is equal to orhigher than a predetermined lockout level for a predetermined timeperiod. The lock-in state refers to the state that the vertical syncsignal VS and the vertical sync signal AFCVS2 are not out of phase witheach other, in which the phase error signal PE is equal to or lower thana predetermined lock-in level (value corresponding to 1H, for example)for a predetermined time period.

[0176]FIG. 18 is a block diagram of an example of the vertical syncsignal phase detection circuit 130 in FIG. 16. As shown in FIG. 18, thevertical sync signal phase detection circuit 130 includes an absolutevalue circuit 131, a hold circuit 132, a lockout comparator circuit 133,a lockout counter 134, a lockout decision circuit 135, a lock-incomparator circuit 136, a lock-in counter 137, a lock-in decisioncircuit 138 and a logic circuit 139.

[0177] The absolute value circuit 131 receives the phase error signal PEoutput from the phase comparator circuit 21. The hold circuit 132, thelockout counter 134 and the lock-in counter 137 receive the verticalsync signal VS and the clock CL having a frequency fs.

[0178] The absolute value circuit 131 obtains the absolute value Z ofthe phase error signal PE and outputs the result to the hold circuit132. The hold circuit 132 latches the output Z of the absolute valuecircuit 131 when receiving a pulse of the vertical sync signal VS insynchronization with the clock CL, and holds the latched value untilreceiving the next pulse of the vertical sync signal VS and furtherreceiving a pulse of the clock CL. The hold circuit 132 outputs the heldvalue Y1 to the lockout comparator circuit 133 and the lock-incomparator circuit 136.

[0179] The lockout comparator circuit 133 compares the output Y1 of thehold circuit 132 with a constant E, and outputs the result to thelockout counter 134. The output of the lockout comparator circuit 133 is“1” when Y1≧E and otherwise “0”, for example.

[0180] The lockout counter 134 increments in synchronization with theclock CL when lo receiving a pulse of the vertical sync signal VS in thecase that the output of the lockout comparator circuit 133 is “1”(Y1>E), and holds the value until receiving the next pulse of thevertical sync signal VS and further receiving a pulse of the clock CL.The lockout counter 134 stops counting once its count value Y2 reachesthe maximum countable value.

[0181] The lockout counter 134 resets the count value to “0” insynchronization with the clock CL when receiving a pulse of the verticalsync signal VS in the case that the output of the lockout comparatorcircuit 133 is “0” (Y1<E). The lockout counter 134 outputs the countvalue Y2 to the lockout decision circuit 135.

[0182] The lockout decision circuit 135 compares the count value Y2 ofthe lockout counter 134 with a constant F, to obtain the comparisonresult of “1” when Y2≧F and otherwise “0”, for example, as a lockoutsignal. The lockout decision circuit 135 then differentiates the lockoutsignal to generate a lockout differential pulse Y3 indicating the timingof the leading edge of the pulse of the lockout signal, and outputs theresult to the logic circuit 139.

[0183] The lock-in comparator circuit 136 compares the output Y1 of thehold circuit 132 with a constant G, and outputs the result to thelock-in counter 137. The output of the lock-in comparator circuit 136 is“1” when Y1≦G and otherwise “0”, for example.

[0184] The lock-in counter 137 increments in synchronization with theclock CL when receiving a pulse of the vertical sync signal VS in thecase that the output of the lock-in comparator circuit 136 is “1”(Y1≦G), and holds the value until receiving the next pulse of thevertical sync signal VS and further receiving a pulse of the clock CL.The lock-in counter 137 stops counting once its count value Y4 reachesthe maximum countable value. The lock-in counter 137 resets the countvalue to “0” in synchronization with the clock CL when receiving a pulseof the vertical sync signal VS in the case that the output of thelock-in comparator circuit 136 is “0” (Y1>G). The lockout counter 137outputs the count value Y4 to the lock-in decision circuit 138.

[0185] The lock-in decision circuit 138 compares the count value Y4 ofthe lock-in counter 137 with a constant J, to obtain the comparisonresult of “1” when Y4≧J and otherwise “0”, for example, as a lock-insignal. The lock-in decision circuit 138 then differentiates the lock-insignal to generate a lock-in differential pulse Y5 indicating the timingof the leading edge of the pulse of the lock-in signal, and outputs theresult to the logic circuit 139.

[0186] The logic circuit 139 conducts logic operation of the output Y3of the lockout decision circuit 135 and the output Y5 of the lock-indecision circuit 138, and outputs the result as the decision signal DS2.Specifically, the logic circuit 139 outputs “1” when receiving thelockout differential pulse Y3 from the lockout decision circuit 135, and“0” when receiving the lock-in differential pulse Y5 from the lock-indecision circuit 138. For example, the logic circuit 139 is a set-resetflipflop that is set with the lockout differential pulse Y3 and resetwith the lock-in differential pulse Y5.

[0187]FIG. 19 is a timing chart showing generation of the lockoutdifferential pulse by the vertical sync signal phase detection circuit130 in the case that the vertical sync signal VS goes out of phaselargely. FIG. 20 is a timing chart showing operation of the verticalsync signal phase detection circuit 130 in the case that noise entersthe vertical sync signal VS. The operation of the vertical sync signalphase detection circuit 130 will be described with reference to FIGS. 17to 20.

[0188] In this embodiment, assume, as an example, that the clockfrequency (sampling frequency) fs is 27 MHz, the period of the verticalsync signal VS in the steady state is T, the pulse interval of thevertical sync signal VS given when the signal goes out of phase largelyis T″, and the constant F is “2”. Assume also that the AFC circuit 120is in the steady state and the period of the vertical sync signal AFCVS2output from the AFC circuit 120 is also T. Suppose the count value Y2 ofthe lockout counter 134 is “0” and the selector 126 selects the outputof the LPF 22 having slower transient response.

[0189] When the phase error signal PE output from the AFC circuit 120has a width of 36 bits, for example, the output Z of the absolute valuecircuit 131 can be any value in the range of −235 to +235−1. In thiscase, the constants E and G are set at 09c000000h and 04e000000h,respectively, for example.

[0190] The pulse interval of the vertical sync signal VS may momentarilybe T″ during power-on, scene switching and the like, as shown in FIG.19. In this event, the phase comparator circuit 21 calculates andoutputs the phase difference between the vertical sync signal VS and thevertical sync signal AFCVS2 as the phase error signal PE.

[0191] The absolute value circuit 131 obtains the absolute value of thephase error signal PE and outputs the result to the hold circuit 132.The hold circuit 132 latches the output Z of the absolute value circuit131 at the timing of the vertical sync signal VS, holds the latchedvalue and outputs the result (value Y1).

[0192] The lockout comparator circuit 133 determines that the output Y1of the hold circuit 132 is larger than the lockout level E, and outputs“1” to the lockout counter 134. Receiving the output “1” of the lockoutcomparator circuit 133, the lockout counter 134 increments whenreceiving a pulse of the vertical sync signal VS and outputs “1”.

[0193] The AFC circuit 120 makes the timing of the vertical sync signalAFCVS2 closer to the timing of the vertical sync signal VS in responseto the phase error signal PE. Therefore, the absolute value of the phaseerror signal PE gradually decreases. Nevertheless, if Y1≧E is stillsatisfied when the next pulse of the vertical sync signal VS is input,the lockout counter 134 further increments and outputs “2” to thelockout decision circuit 135 as the count value Y2. The lockout counter134 will no more increment once the count value Y2 reaches “2”, forexample.

[0194] Having the count value Y2 of “2” that is equal to the constant F,the lockout decision circuit 135 decides that it is in the lockout stateand turns the lockout signal to “1”. With the change of the lockoutsignal from “0” to “1”, the lockout decision circuit 135 outputs thelockout differential pulse Y3 to the logic circuit 139, and the logiccircuit 139 outputs “1” as the decision signal DS2. In response to this,the selector 126 selects the output of the LPF 122 having fastertransient response. This makes the response of the AFC circuit 120faster, and thus makes the change of the absolute value Z output fromthe absolute value circuit 131 faster.

[0195] Thereafter, when Y1<E is satisfied, the output of the lockoutcomparator circuit 133 becomes “0”, and thus the lockout counter 134resets the count value Y2 to “0”. The lockout decision circuit 135decides that it is not in the lockout state and turns the lockout signalto “0”. The output Y1 of the hold circuit 132 continues decreasingtoward “0”.

[0196] As described above, when the lockout state is detected, theresponse of the AFC circuit 120 is made faster. This makes the timing ofthe vertical sync signal AFCVS2 match with the timing of the verticalsync signal VS swiftly.

[0197] The case shown in FIG. 20, in which the vertical sync signal VSmomentarily goes out of phase largely due to noise entering the verticalsync signal VS, will be described. In this case, while the output Y1 ofthe hold circuit 132 momentarily becomes a large value, the part of thevertical sync signal VS other than the noise portion remains the steadystate with the period T kept unchanged. Therefore, the timing of thevertical sync signal AFCVS2 output from the AFC circuit 120 does notchange so much, and thus the phase error signal PE converges to “0”swiftly.

[0198] The lockout counter 134 increments the count value Y2 to “1”, butis soon reset because Y1<E is resumed. Therefore, the lockout decisioncircuit 135 does not detect the lockout state and thus does not changethe lockout signal, generating no lockout differential pulse Y3. Thevertical sync signal generator 110 continue selecting and outputting thevertical sync signal AFCVS2 as the vertical sync signal GVS2. Thus, thevertical sync signal GVS2 is hardly affected by the noise.

[0199] If the constant F is set at “1”, the lockout decision circuit 135will decide that it is in the lockout state when noise enters thevertical sync signal VS. In this case, the vertical sync signalgenerator 110 will select and output the noise-contained vertical syncsignal VS as the vertical sync signal GVS2. To avoid influence of noise,therefore, the constant F should be “2” or more.

[0200]FIG. 21 is a timing chart showing generation of the lock-indifferential pulse by the vertical sync signal phase detection circuit130 in the case that the vertical sync signal VS goes out of phaselargely. Assume, as an example, that the constant J is “7”. As in thecase of FIG. 19, the case that the pulse interval of the vertical syncsignal VS momentarily becomes T″ will be described. The output Y1 of thehold circuit 132 is the same as that in the case of FIG. 19.

[0201] Assume that the count value of the lock-in counter 137 is “7”.When the pulse interval of the vertical sync signal VS becomes T″raising the output Y1 of the hold circuit 132 to a value equal to orlarger than the lock-in level G, the lock-in comparator circuit 136outputs “0” to the lock-in counter 137. The lock-in counter 137,receiving the output “0” of the lock-in comparator circuit 136, resetsthe count and outputs “0” as the count value Y4. Receiving the countvalue Y4 smaller than the constant J of “7”, the lock-in decisioncircuit 138 decides that it is not in the lock-in state and turns thelock-in signal to “0”.

[0202] The AFC circuit 120 makes the timing of the vertical sync signalAFCVS2 closer to the timing of the vertical sync signal VS in responseto the phase error signal PE. Therefore, the absolute value of the phaseerror signal PE gradually decreases. When Y1<G is satisfied, the lock-incounter 137 increments every input of the pulse of the vertical syncsignal VS, and outputs the count value Y4 to the lock-in decisioncircuit 138. The lock-in counter 137 will no more increment once thecount value Y4 reaches “7”, for example.

[0203] Having the count value Y4 of “7” that is equal to the constant J,the lock-in decision circuit 138 decides that it is in the lock-in stateand turns the lock-in signal to “1”. With the change of the lock-insignal from “0” to “1”, the lock-in decision circuit 138 outputs thelock-in differential pulse Y5 to the logic circuit 139, and the logiccircuit 139 outputs “0” as the decision signal DS2. In response to this,the selector 126 selects the output of the LPF 22 having slowertransient response. This makes the operation of the AFC circuit 120stable. With the decision signal DS of “0”, the selector 12 in FIG. 16selects and outputs the vertical sync signal AFCVS2 output from the AFCcircuit 120 as the vertical sync signal GVS2.

[0204] As described above, when the lock-in state is detected, switchingis made to use the LPF 22 having slower transient response, and thus thevertical sync signal AFCVS2 can be stabilized.

[0205]FIG. 22 is a timing chart showing operation of the logic circuit139 in FIG. 18. If the vertical sync signal VS goes out of phase largelyand the phase error signal PE continues being large, the lockoutdecision circuit 135 decides that it is in the lockout state and outputsthe lockout differential pulse Y3. The logic circuit 139 then turns thedecision signal DS2 to “1”. The selector 12 of the vertical sync signalgenerator 110, having the decision signal DS2 of “1”, selects andoutputs the vertical sync signal VS as the vertical sync signal GVS2. Inthis way, the vertical sync signal GVS2 free from being out of phasewith the input luminance signal can be obtained.

[0206] Having the decision signal DS2 of “1”, the selector 126 of theAFC circuit 120 selects the output of the LPF 122 having fastertransient response. This makes the phase of the vertical sync signalAFCVS2 swiftly closer to the phase of the vertical sync signal VS, andthus makes the phase error signal PE small.

[0207] When the phase error signal PE remains small for a certain timeperiod, the lock-in decision circuit 138 outputs the lock-indifferential pulse Y5, and thus the logic circuit 139 turns the decisionsignal DS2 to “0”. The selector 12 of the vertical sync signal generator110, having the decision signal DS2 of “0”, selects and outputs thevertical sync signal AFCVS2 as the vertical sync signal GVS2. Since thephase difference between the vertical sync signal AFCVS2 and thevertical sync signal VS is very small at this time, there will be nodisorder of the vertical sync signal GVS2 during the switching of theselector 12.

[0208] Having the decision signal DS2 of “0”, the selector 126 of theAFC circuit 120 selects the output of the LPF 22 having slower transientresponse. Therefore, the vertical sync signal AFCVS2 having a stableperiod can be obtained as the vertical sync signal GVS2.

[0209] As described above, the vertical sync signal generator of thisembodiment outputs the vertical sync signal AFCVS during normaloperation, and outputs the vertical sync signal VS, in place of thevertical sync signal AFCVS, when detecting that the vertical sync signalVS and the vertical sync signal AFCVS2 are out of phase with each other,during power-on, scene switching and the like. Therefore, during normaloperation, a vertical sync signal stable in frequency and free frompulse missing can be provided. In addition, in the case that thevertical sync signal VS and the vertical sync signal AFCVS2 are out ofphase with each other, the LPF having faster transient response is used,so that the vertical sync signal AFCVS2 can be swiftly drawn intosynchronization.

[0210] In the embodiments described above, the video signal of the NTSCsystem was used. However, the present invention can also be applied tovideo signals of other systems.

1. A vertical sync signal generator comprising: a vertical sync signalseparation circuit for separating a vertical sync signal of an inputluminance signal and outputting the separated signal as a first verticalsync signal; an automatic frequency control circuit for receiving thefirst vertical sync signal, generating a second vertical sync signalhaving a repeat frequency corresponding with an average repeat frequencyof the first vertical sync signal, and outputting the generated signal;a vertical sync signal phase detection circuit for detecting whether ornot the first vertical sync signal has two different periods repeatedalternately, and outputting the detection result as a decision signal;and a selector for receiving the first and second vertical sync signals,selecting the first vertical sync signal when the decision signalindicates that the first vertical sync signal has two different periodsrepeated alternately and otherwise selecting the second vertical syncsignal, and outputting the selected signal.
 2. The vertical sync signalgenerator of claim 1, wherein the automatic frequency control circuitcomprises: an integrator circuit of m bits (m is a natural number) foraccumulating input values; a phase comparator circuit for sampling anoutput of the integrator circuit at the timing of the first verticalsync signal and outputting a difference between a sampled value and apredetermined value; a low pass filter for allowing passing of alow-frequency component out of the output of the phase comparatorcircuit; an adder circuit for adding a constant to an output of the lowpass filter and outputting the result to the integrator circuit; and adifferential circuit for differentiating the most significant bit of theintegrator circuit and outputting the second vertical sync signal at thetiming of the resultant edge.
 3. The vertical sync signal generator ofclaim 1, wherein the vertical sync signal phase detection circuitcomprises: a V period counter reset at the timing of the first verticalsync signal, for counting the number of pulses of a clock and outputtingthe count value; a first hold circuit for latching the output of the Vperiod counter at the timing of the first vertical sync signal,outputting the latched value, and holding the output until nextlatching; a first subtractor circuit for calculating a differencebetween the output of the V period counter and the output of the firsthold circuit and outputting the result; a first absolute value circuitfor obtaining an absolute value of the output of the first subtractorcircuit and outputting the result; a second hold circuit for latchingthe output of the first absolute value circuit at the timing of thefirst vertical sync signal, outputting the latched value, and holdingthe output until next latching; a second subtractor circuit forcalculating a difference between the output of the first absolute valuecircuit and the output of the second hold circuit and outputting theresult; a second absolute value circuit for obtaining an absolute valueof the output of the second subtractor circuit and outputting theresult; a first comparator circuit for comparing the output of the firstabsolute value circuit with a first constant and outputting the result;a second comparator circuit for comparing the output of the secondabsolute value circuit with a second constant and outputting the result;and a logic circuit for conducting logic operation of the output of thefirst comparator circuit and the output of the second comparator circuitand outputting the result as the decision signal.
 4. A video signalprocessor comprising: a vertical sync signal generator; a horizontalsync signal separation circuit for separating a horizontal sync signalof an input luminance signal and outputting the separated signal; and aframe sync circuit having a frame memory, for generating a write addressin a predetermined order based on an output of the vertical sync signalgenerator, the horizontal sync signal and a write clock, and writing aninput video signal into the frame memory according to the write address,as well as generating a read address in the same order as the order ofthe write address based on a read clock, reading the signal from theframe memory according to the read address, and outputting the readsignal as a standard video signal, wherein the vertical sync signalgenerator comprises: a vertical sync signal separation circuit forseparating a vertical sync signal of the input luminance signal andoutputting the separated signal as a first vertical sync signal; anautomatic frequency control circuit for receiving the first verticalsync signal, generating a second vertical sync signal having a repeatfrequency corresponding with an average repeat frequency of the firstvertical sync signal, and outputting the generated signal; a verticalsync signal phase detection circuit for detecting whether or not thefirst vertical sync signal has two different periods repeatedalternately, and outputting the detection result as a decision signal;and a selector for receiving the first and second vertical sync signals,selecting the first vertical sync signal when the decision signalindicates that the first vertical sync signal has two different periodsrepeated alternately and otherwise selecting the second vertical syncsignal, and outputting the selected signal, and when the rate at whichthe write address changes and the rate at which the read address changesare different from each other, the frame sync circuit controls the writeinto 10 the frame memory or the read from the frame memory so thatduring read of a signal of a given frame from the frame memory, read ofa signal of a frame other than the given frame caused by addressovertaking does not occur.
 5. The video signal processor of claim 4,wherein the frame sync circuit has at least two frame memories, andcomprises: a write control circuit for generating a write selectionsignal for selecting a frame memory into which a signal is written, fromthe two frame memories, and the write address for the selected framememory, based on the output of the vertical sync signal generator, thehorizontal sync signal and the write clock, and outputting the generatedsignal and address; a read control circuit for counting the read clock,generating the read address for the two frame memories according to theresultant count value, and outputting the generated address; and askip/hold control circuit for generating a skip/hold control signal forselecting a frame memory from which a signal is read, based on thetrends of changes of the write address and the read address, andoutputting the generated signal, and the frame sync circuit writes aninput video signal into the frame memory selected with the writeselection signal according to the write address, and also reads a signalfrom the frame memory selected with the skip/hold control signalaccording to the read address and outputs the signal as the standardvideo signal.
 6. The video signal processor of claim 4, wherein theframe sync circuit comprises: a line memory for delaying an input videosignal by a time corresponding to a predetermined number of lines andoutputting the delayed signal; a write control circuit for generatingthe write address for the frame memory based on the output of thevertical sync signal generator, the horizontal sync signal and the writeclock, and outputting the generated address; a read control circuit forcounting the read clock, generating the read address for the framememory according to the resultant count value, and outputting thegenerated address; and a skip/hold control circuit for generating askip/hold control signal for controlling so that either one of the inputvideo signal and the output of the line memory is selected based on adifference between the write address and the read address and writteninto the frame memory, the frame sync circuit writes one of the inputvideo signal and the output of the line memory selected with theskip/hold control signal into the frame memory according to the writeaddress, and also reads a signal from the frame memory according to theread address and outputs the signal as the standard video signal.
 7. Thevideo signal processor of claim 4, further comprising: a datamultiplexer circuit for adding a data group representing a start mark,an end mark and a blanking time to data of each line of the standardvideo signal output from the frame sync circuit.
 8. A vertical syncsignal generator comprising: a vertical sync signal separation circuitfor separating a vertical sync signal of an input luminance signal andoutputting the separated signal as a first vertical sync signal; anautomatic frequency control circuit for receiving the first verticalsync signal, generating a second vertical sync signal having a repeatfrequency corresponding with an average repeat frequency of the firstvertical sync signal and a phase error signal indicating a phasedifference between the first vertical sync signal and the secondvertical sync signal, and outputting the generated signals; a verticalsync signal phase detection circuit for detecting whether or not thefirst vertical sync signal and the second vertical sync signal are outof phase with each other based on the phase error signal, and outputtingthe detection result as a decision signal; and a selector for receivingthe first and second vertical sync signals, selecting the first verticalsync signal when the decision signal indicates that the first verticalsync signal and the second vertical sync signal are out of phase witheach other and otherwise selecting the second vertical sync signal, andoutputting the selected signal.
 9. The vertical sync signal generator ofclaim 8, wherein the automatic frequency control circuit comprises: anintegrator circuit of m bits for accumulating input values; a phasecomparator circuit for sampling an output of the integrator circuit at atiming of the first vertical sync signal and outputting a differencebetween a sampled value and a predetermined value as the phase errorsignal; a first low pass filter for allowing passing of a low-frequencycomponent out of the phase error signal; a second low pass filter forallowing passing of the low-frequency component and a component having ahigher frequency than the low-frequency component out of the phase errorsignal; a filter selector for selecting an output of the second low passfilter when the decision signal indicates that the first vertical syncsignal and the second vertical sync signal are out of phase with eachother and otherwise selecting an output of the first low pass filter,and outputting the selected signal; an adder circuit for adding aconstant to the output of the filter selector and outputting the resultto the integrator circuit; and a differential circuit fordifferentiating the most significant bit of the integrator circuit andoutputting the second vertical sync signal at a timing of the resultantedge.
 10. The vertical sync signal generator of claim 8, wherein thevertical sync signal phase detection circuit comprises: an absolutevalue circuit for obtaining an absolute value of the phase error signaland outputting the result; a hold circuit for latching the output of theabsolute value circuit at the timing of the first vertical sync signal,outputting the latched value, and holding the output until nextlatching; a lockout comparator circuit for comparing the output of thehold circuit with a first constant and outputting the comparison result;a lockout counter for counting the number of pulses of the firstvertical sync signal when the output of the lockout comparator circuitindicates that the output of the absolute value circuit is equal to orlarger than the first constant, and outputting the resultant countvalue; a lockout decision circuit for outputting a lockout differentialpulse when the count value of the lockout counter is equal to a secondconstant; a lock-in comparator circuit for comparing the output of thehold circuit with a third constant and outputting the comparison result;a lock-in counter for counting the number of pulses of the firstvertical sync signal when the output of the lock-in comparator circuitindicates that the output of the absolute value circuit is equal to orsmaller than the third constant, and outputting the resultant countvalue; a lock-in decision circuit for outputting a lock-in differentialpulse when the count value of the lock-in counter is equal to a fourthconstant; and a logic circuit for outputting the decision signalindicating that the first vertical sync signal and the second verticalsync signal are out of phase with each other when the lockout decisioncircuit outputs the lockout differential pulse, and outputting thedecision signal indicating that the first vertical sync signal and thesecond vertical sync signal are not out of phase with each other whenthe lock-in decision circuit outputs the lock-in differential pulse.